DMAREQ1

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Interpret as DMAREQ1

SCT DMA request 1 register

DEV_1	If bit n is one, event n sets DMA request 1 (event 0 = bit 0, event 1 = bit 1,…, event 15 = bit 15).
RESERVED	Reserved
DRL1	A 1 in this bit makes the SCT set DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
DRQ1	This read-only bit indicates the state of DMA Request 1.

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